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This document focuses on the timing requirement it explains the timing- driven FPGA implementation processes and shows how to tackle timing issues when timing closure becomes problematic.Ģ. This can require hard work for high-speed design in order to close timing using various techniques (including the trade-off between throughput and latency, appropriate timing constraint adjustments, etc.) and running through multiple processing iterations including Synthesis, MAP and PAR. More often, FPGA designers deal with the timing requirement to make sure that the design runs at the required clock speed. For example, high throughput usually means more pipelining, which increases the latency low latency usually requires longer combinatorial paths, which removes pipelines, and this can reduce the throughput and clock speed. Throughput the average rate of the valid output delivered per clock cycle Latency the amount of the time required when the valid output is available after the input arrives, usually measured in the number of clock cycles Throughput and latency are usually related to the design architecture and application, and they need to be traded off between each other based on the system requirement. This is defined through the target clock period (or clock frequency) and a few other constraints. There are generally three types of speed requirement in an FPGA design: Timing requirement how fast or slow a design should run. Timing Closure 1 Timing Closure Introduction Every design has to run at a certain speed based on the design requirement.